Hey AI, Generate Me a Hardware Code! Agentic AI-based Hardware Design & Verification

📝 Paper Summary

Agentic AI for Hardware EDA (Electronic Design Automation)

A multi-agent system collaborates with human experts and industry EDA tools to automate hardware code generation and formal verification, achieving over 95% coverage where zero-shot methods fail.

Core Problem

RTL design and verification are bottlenecks consuming 60% of chip development time; existing LLM approaches suffer from high failure rates (~60%) and cannot interact with verification tools.

Why it matters:

Simulation-based verification is computationally expensive and slow as IC complexity scales
Zero-shot LLMs often generate non-synthesizable code or hallucinations, lacking the iterative refinement needed for functional correctness
Manual translation of specifications to properties is error-prone and labor-intensive

Concrete Example: In the ECC (Error Correction Code) design, a zero-shot LLM approach generated code with severe lint errors and functional placeholders. The proposed agents identified these issues via tool feedback, and a human expert intervened for under 30 minutes to fix logic gaps, achieving functional RTL.

Key Novelty

Agentic Hardware Design with Tool-in-the-Loop

Decomposes hardware creation into Planning, Development, and Execution phases handled by specialized agents (Design Lead, Verification Engineer, Critic)
Integrates agents directly with industrial EDA tools (SpyGlass, JasperGold) to validate code and assertions autonomously
Incorporates a structured Human-in-the-Loop protocol where agents escalate specific ambiguities or persistent errors to humans rather than failing silently

Architecture

The 3-phase Agentic AI Hardware Design Methodology (Planning, Development, Execution).

Evaluation Highlights

Achieved average formal coverage of 97.73% across five open-source designs using MAS + HITL, compared to ~69.85% for zero-shot baselines
Attained 100% assertion pass rate on all benchmarks after iterative refinement
Reduced manual verification effort significantly, requiring only 15–40 minutes of HITL intervention per design to reach sign-off quality

Breakthrough Assessment

8/10

Significant step in applying agentic AI to hardware by integrating real EDA tools and formal verification loops, moving beyond simple code generation to rigorous validation.

⚙️ Technical Details

Problem Definition

Setting: End-to-end generation of Register Transfer Level (RTL) code and SystemVerilog Assertions (SVA) from natural language specifications

Inputs: Natural language specification document (requirements, interfaces, FSM details)

Outputs: Verified RTL code, SystemVerilog Assertions (SVA), and a formal coverage report

Pipeline Flow

Phase 1: Planning (Spec parsing -> Microarchitecture & Verification Plan)
Phase 2: Development (Code Generation & Critique)
Phase 3: Execution (EDA Tool Run & Analysis)

System Modules

Design Lead Agent (Planning)

Parse specifications to produce microarchitecture details (datapath, FSM, reset strategies)

Model or implementation: GPT-4o

Verification Lead Agent (Planning)

Interpret specifications to generate a Verification Plan (vPlan)

Model or implementation: GPT-4o

RTL Agent (Development)

Generate SystemVerilog modules based on microarchitecture guidelines

Model or implementation: GPT-4o

Formal Verification Agent (Development)

Translate vPlan entries into SystemVerilog Assertions (SVA)

Model or implementation: GPT-4o

Code Executor Agent

Interface with industry EDA tools to validate RTL and Assertions

Model or implementation: Tool-Use Wrapper (connects to SpyGlass/JasperGold)

Novel Architectural Elements

Integration of a 'Code Executor' agent capable of driving proprietary EDA tools (SpyGlass, JasperGold) and parsing their logs to feed back into the chat
Explicit 3-phase workflow (Planning -> Development -> Execution) decoupling architectural reasoning from syntax generation

Modeling

Base Model: GPT-4o

Compute: Inference only; HITL interventions took 15-40 minutes per design. Specific GPU/TPU usage not reported.

Comparison to Prior Work

vs. Zero-shot: Uses Multi-Agent System (MAS) with tool feedback loops and human intervention, achieving ~98% coverage vs ~70%
vs. AIVRIL/VeriAssist: Focuses on Formal Verification (mathematical proof) rather than just Simulation, and integrates HITL for ambiguity resolution

Limitations

Relies on commercial/proprietary EDA tools (SpyGlass, JasperGold), limiting accessibility
Higher temperature settings (0.8) caused randomness and syntax errors, requiring more human intervention
Requires engineers to understand AI reasoning patterns to effectively intervene (cognitive load trade-off)

Reproducibility

Code availability is not provided in the paper. The system relies on proprietary EDA tools (Synopsys SpyGlass, Cadence JasperGold) which are closed-source commercial software.

📊 Experiments & Results

Evaluation Setup

Design and verify 5 hardware modules using the MAS framework, measuring code quality and verification coverage

Benchmarks:

OpenCores Designs (Hardware Design (CRC, ECC, FIFO))
VerilogEval Designs (Hardware Design (Lemming, Timer))

Metrics:

Lint Errors
Logical Accuracy
Formal Coverage (%)
Counter-Example (CEX) Count
HITL Effort (Time)
Statistical methodology: Not explicitly reported in the paper

Key Results

Benchmark	Metric	Baseline	This Paper	Δ
Formal Property Generation results (Table I) showing the final coverage and assertion status after Human-in-the-Loop (HITL) intervention.
CRC (OpenCores)	Formal Coverage	Not reported in the paper	100	Not reported in the paper
ECC (OpenCores)	Formal Coverage	Not reported in the paper	95.90	Not reported in the paper
FIFO (OpenCores)	Formal Coverage	Not reported in the paper	97.29	Not reported in the paper
Average across all designs	Formal Coverage	69.85	97.73	27.88

Experiment Figures

Comparison of Formal Coverage % between Zero-shot approach and the proposed MAS approach.

Main Takeaways

Zero-shot approaches struggle with complex sequential logic, often failing to compile or achieving low coverage (~70%).
The Multi-Agent System (MAS) autonomously clears most lint and syntax errors, but Human-in-the-Loop (HITL) is essential for resolving logic gaps and ambiguities.
Higher temperature (0.8) increases diversity but introduces severe lint errors; lower temperature (0.2) is more stable for RTL generation.
Human intervention is time-efficient (15-40 mins) and high-leverage, focusing on conceptual issues rather than writing boilerplate code.

📚 Prerequisite Knowledge

Prerequisites

Digital Logic Design (FSMs, Datapaths)
SystemVerilog language
Formal Verification concepts

Key Terms

RTL: Register Transfer Level—a level of abstraction used in describing the operation of a digital circuit (like code for chips)

EDA: Electronic Design Automation—software tools used to design and verify integrated circuits

SVA: SystemVerilog Assertions—statements used to verify that a design's behavior matches its specification

HITL: Human-in-the-Loop—a model where human interaction is required to resolve ambiguities or errors the AI cannot handle

MAS: Multi-Agent System—a computerized system composed of multiple interacting intelligent agents

Linting: Static analysis to flag syntax errors, coding standard violations, or potential bugs in code

Formal Verification: Using mathematical methods to prove that a system satisfies certain properties (as opposed to just simulating it)

CEX: Counter-Example—a specific scenario found by a formal verification tool where the design violates a property